1. Field of the Invention
This present invention is related in general to methods and structures for power amplifier systems. More particularly, the invention is directed to methods and structures for stabilizing power amplifier performance.
2. Description of the Prior Art and Related Background Information
Due to the temperature dependence of transistor parameters, the performance of solid state devices changes considerably with temperature. A drift in transconductance is known to decrease the linear gain but the effects are far reaching and cause changes in nonlinear transfer characteristics of the power amplifier (“PA”) subassembly in general. As an example, in a CMOS transistor, there is a drift in gate threshold voltage of around 2 mV/° C. Silicon LDMOS transistors, which are widely used in cellular communications infrastructure, exhibit such behavior. A similar effect can be identified in current-controlled current source devices such as bipolar transistors and other field effect transistors (“FET”).
Most amplifier circuits compensate for this drift by employing bias-compensating circuitry. These circuits generate a gate bias voltage that varies with temperature having a gradient opposite to that of the amplifying device. While such prior art remedies are widely used in practice, the amplifier characteristics still change considerably. In a typical linearized multi-stage PA system, the magnitude of linear gain drift can be as large as 10 dB over the system's operating temperatures. This linear gain drop is compensated by automatically increasing the input drive level. However, the deterioration in intermodulation distortion (“IMD”) performance and increase of out of band emissions must be compensated by the linearizer. A well-designed linearization system can constantly monitor the output and dynamically compensate for temperature-related changes.
A closer look at the prior art for bias circuit compensation points to analog solutions. In one solution, an n-p-n transistor is placed very close to the amplifying device to have a near identical temperature exposure. Resistors define the slope of the compensation. (See, for example, Electronic Devices and Circuits: Principles and Applications, by Deshpande, Mc Graw-Hill, reprint 2008, ISBN10:0-07-061711-2).
More recently, with the aid of microprocessors and digital potentiometers, the bias circuits have changed considerably. (See Intersil, X96011 Sensor Bias Conditioner IC, Application note AN174.2, http://www.intersil.com/data/an/an174.pdf, Apr. 20, 2006). In a microprocessor-controlled bias circuit, the VGS (or VBE) variation vs. temperature is characterized and the compensated values are stored in a microprocessor's nonvolatile memory. A temperature sensor is used in proximity to the RF power transistors and feeds the temperature data back to the microcontroller. Based on this information the microcontroller calculates the appropriate gate bias voltage and applies this voltage directly to the RF transistor gate.
A hybrid of the above two approaches is also occasionally used. In such a scenario the microcontroller sets the initial quiescent bias value and provides the appropriate switching sequences. A p-n-p or n-p-n transistor is used for the temperature drift compensation in an analog circuit.
In another more recent approach that is commercially available, all the functions needed to control the PA chain are designed into a single application-specific integrated circuit (“ASIC”). (See Maxim, MAX1386, Dual RF LDMOS Bias Controllers with I2C/SPI Interface, http://www.maxim-ic.com/datasheet/index.mvp/id/5155/t/al). Such a solution achieves gate bias voltage accuracy to within a few microvolts of resolution for self-calibration. An EEPROM is organized to store a lookup table and register information required to start up and maintain the bias conditions over a wide range of temperatures and output powers. In this approach rather than only measuring device package temperature, the integrated bias circuit monitors device current (ID), voltage, and temperature, logically deciding if the DAC output voltage should be adjusted to maintain the bias setting. Such bias controllers offer self-calibration modes to minimize error over time and with variations in temperature and supply voltage.
The application of the bias-temperature controllers outlined above helps with device dynamics and as outlined previously this operation is totally independent of the linearization engine running in parallel. It might be reasonable to claim that the bias stabilization circuitries assist PA linearization in a nearly steady-state thermal condition but they can be unhelpful in initial phase of operation or in a PA-DPD's startup process.
Accordingly, a need exists to stabilize power amplifier performance.